1. Field of the Invention
This invention generally relates to integrated circuits (ICs) and, more particularly, to a post-production method for patterning an IC etch mask, to support the selective etching of packaged and unpackaged. IC die for investigation or repair.
2. Description of the Related Art
IC production facilities are established so that thousands of fragile parts can be safely processed in a short amount of time, with little human intervention. IC dice are parallel processed on a wafer, and each die may include thousands, or even millions of electrical components, such as transistors and resistors, distributed over multiple interconnected layers. Typically, an IC die is tested after fabrication, and many “internal” test points are exposed at this point in the process. After attachment to an IC package, for example using an epoxy adhesive, only the package external interfaces, or pins are accessible.
While it is rarely cost effective to repair an IC die after it has been assembled into a package, there are many circumstances where it desirable to reverse engineer, perform fault analysis, or access an internal test point to monitor performance under realistic load conditions. Typically, it is easier to access the backside of the IC, which is the first layer of IC die circuitry. Therefore, it is necessary to remove a region of the bulk silicon (Si) wafer upon which the IC has been fabricated. Depending on the package style, the package or part of the package may be removed to access the bulk Si wafer.
Once the region of interest is exposed, a “picoprobe”, which is a probe with a field effect transistor (FET) input and very fine tip, can be used to measure electrical signals. Alternately, temperature measurements can be made, or a photon emission microscope (PEM) may be used to measure light being emitted from operating transistors. Further, a scanning electron-beam microscope (SEM) may be used to measure electron flow.
However, it is difficult to precisely locate a window through the bulk Si to the backside of the IC die. It is also difficult to efficient make such a window, without damaging the IC die, in a time effective manner. Although laser and chemical etching processes may be used to form openings in thin-film passivation layers, generally a focused ion beam (FIB) is the tool of choice for etching through the relatively thick bulk Si layer.
FIB systems have a fine resolution, better than 0.1 microns, and can forms holes with an aspect ratio of up to 18:1. A FIB is similar to a scanning electron microscope, but uses to focused beam of gallium ions instead of electrons. The ions are accelerated to an energy of up to 50 keV, and focused with an electrostatic lenses. A FIB can deliver tens of nanoamps of current to a selected region, or can image die region with a spot size on the order of a few nanometers.
The FIB ions are inherently destructive, as they sputter atoms from the surface they strike. As a result, the FIB can be used as a micro-machining tool, to etch features at as very fine scale. Further. FIB can be used to deposit material via ion beam induced deposition of FIB-assisted chemical vapor deposition (CVD). Thus, FIB is used to modify an existing IC, remove electrical connections, or deposit a conductive metal.
To form a window through the bulk Si wafer to the backside of the IC die, the bulk Si wafer is initially thinned using a polishing process. Then, it is typically necessary to use the FIB to form three of four alignment holes to find alignment markings. Once the alignment is known, a window can be sputtered to the desired die region. Alternately, the FIB may be accessorized with a con-focal laser to perform the alignment. However, these instruments are very expensive and the etching must be performed one window at a time, which is slow and costly. The selective removal of the bulk silicon on the back of the die is also needed to support other failure analysis techniques such as light emission, thermally induced voltage alteration (TIVA), infrared (IR) imaging, laser voltage probing, picosecond (PICA), and others.
One solution to this problem was presented in U.S. Pat. No. 7,402,469, invented by Joseph Patterson. This method initially irradiates the bulk Si layer to locate an IC die region. In response to irradiating an overlying semi-transparent film with a greater power density, a region of the semi-transparent film is marked. An etch-dam is created around the marked region, so that the bulk Si layer can be selectively etched. Unfortunately, this method requires the application of different materials in separate process steps. Further, the selective etching is a manual process requiring dexterity, which often reduces alignment accuracy.
It would be advantageous if a method existed for forming windows through a Si wafer, to an IC die, that was faster and more efficient than the above-described processes.